COMMODORE SEMICONDUCTOR GROUP a division of Commodore Business Machines, Inc. 950 Rirrenhouse Road. Norristown. PA 19403 215/666-7950 TWX 510-660-4168 NMOS 6500 MICROPROCESSORS THE 6500 MICROPROCESSOR FAMILY CONCEPT The 6500 Series Microprocessors represent the first totally software compatible microprocessor family. This family of products inciudes a range of software compatible microprocessors which provide a selection of addressable memory range, Interrupt input options and on-chip clock oscillators and drivers. All of the microprocessors in the 6500 group are software compatible within the group and are bus compatible with the M6800 product offering. The family includes six microprocessors with on-board clock oscillators and drivers and four microprocessors driven by external clocks. The on-chip clock versions are aimed at high performance, |ow cost applications where single phase inputs, crystal or RC inputs provide the time base. The external clock versions are geared for the multi processor system applications where maximum timing control is mandatory. All versions of the microprocessors are available in 1 MHz, 2 MHz {A suffix on product numbers), 8 MHz ("B suffix on product numbers), and 4 MHz (C" suffix on product numbers) maximum operating frequencies. oO Or o = ad O 0 D Oo ) m * a O O N FEATURES OF THE 6500 FAMILY e Single +5 volt supply e 8 BIT Brdirectional Data Bus e N channel, silicon gate, depletion load e Addressable memory range of up to 05K technology pytes e Eight bit parallel processing e Ready input (for single cycie execution) e 56 Instructions e Direct memory access Capability e Decimal and binary arithmetic e Bus compatible with M6800 e Thirteen addressing modes e Choice of external or on-board clocks e True indexing Capability e 1 MHz, 2 MHz, 3 MHz and 4 MHz operation e Programmable stack pointer e On-the-chip clock options e Variable lengtn stack e External single clock input e Interrupt capability e RC time base input e Non-maskabie !nterrupt e Crystal! time base input e Use with any type or speed memory e Pipeline architeciure MEMBERS OF THE 6500 MICROPROCESSOR ORDER NUMBER (CPU) FAMILY MXS 65SS Microprocessors with On-Chip Clock Oscillator | Mode! Addressable Memory Roo02 o5K Bytes R6503 4K Bytes FREQUENCY RANGE R6504 8K Bytes NO SUFFIX = 1 MHz R6505 4K Bytes A= 2 MHz R6506 4K Bytes | B= 3 MHz R6507 8K Bytes C= 4 MHz Microprocessors with External Two Phase MODEL DESIGNATOR Clock Inputs XX = 02.03.04, ...15 Model Addressable Memory | R6512 65K Bytes PACKAGE DESIGNATOR R6513 4K Bytes C = CERAMIC Ro514 8 Bytes = PLASTIC R6515 4K Bytes 11/85COMMENTS ON THE DATA SHEET Tne data sheet is constructed to review first the basic Common Characteristics features which are common to the general family of microprocessors. subsequent to a review of the family characteristics will be sections devoted to each member of the group with specific features of eacn. COMMON CHARACTERISTICS ADDRESS BUS q REGISTER SECTION CONTROL SECTION > RES IRQ NMI oe byt i- ae iecer INTERRUPT y $$ ____, LOuIG _ INDEX Koy REGISTER || ~ 21yy _ ee _--| LC x 2K fC STACI ~ PON | KJ ogecisier | i4 bOI br IND RUC TION om | gj _| DECODE ALU cS cw I} | i Z x 4] = 4 S ~1 = Tt ACCUMULATOR TIMING | =| | A suns < _ sc. a on CLOCK = LI | PROCESSOR GENERATOR a STATUS | INF T L REGISTER | LATA _-4 LATCH 5 | (UL, _ <_ ; _ _ ATA BUS . INSTRUCTION ~- |_| | BUFFER TT HEGISTER a I 7 TAT VE gr aie | | | fg ). Sane UL Ate - tt D5 BUS =acli Lilit aD a 4 Ve | = " BI Lite Us D- Note: 1. Clock Generator is not included on 6512,13,14.15 6500 Internal Architecture 2. Addressing Capability and control options vary with each of the 6500 Products. those a J LTP CLOCK lLiNPUt YP ib TN} Y. UbLT D . OUT FY UBE ODE boie (G16 15 bd5SU?P 645.07| COMMON CHARACTERISTICS MAXIMUM RATINGS RATING | SYMBOL | SUPPLY VOLTAGE Vec O3to+ 7/0 | | INPUT VOLTAGE vin 0.3 to + 7.0 Vde OPERATING TEMPE RATURE Fa Oto +70 C | STORAGE TEMPERATURE TSTG 55 to + 150 C ifs device contains input protection against damage due to high Static vOitages or electric fields: however. orecautions shouid be taken fo avoid application of voitaaes higher than [he maximum rating. ELECTRICAL CHARACTERISTICS (Vcc = 5.0V + 5%, Vss = 0, TA=0 to+ 70 C) Oo. &, (in) applies to 6512, 13,14, 19; 0 (in) applies to 6502, 03, 04, 05, 06 and 07 | CHARACTERISTIC L SYMBOL MIN. TYP. MAX. 1 Input High Voltage Logic. @. (in) Vss +24 Vcc Vde 2. Din) | VIH Vcc 0.2 ~ Vec+10V | ~~ Vde Input High Voltage RES. NM1, RDY, IRQ. Data, $.O. Vss + 2.0 Vde Inout Low Voitage | Logic. Btn) Vss - 03 Vss +04 Vdc Q.. B> (in) VIL Vss 0.3 Vss 7 02 Vde | 1 { RES. NMI. RDY. IRQ. Data, S.O. Vss +08 Vde Le ear r Input Leakage Current | | (Vin =O to 5.25V. Voc = 5.25V) Logic (Excl. RDY. 5.0} In 2.9 uA Z.. B- tiny 1GQ uA ne } | | | _ Three State (Off State) input Current (Vin = 0.4 to 2.4V, Voc = 3.25V) Data Lines TSI 10 AA Output High Voltage (OW = ~10QuAdC. Vcc = 4./9V) SYNC, Data. AQ-A15. RyW VOH | Vss+24 Vde Out Low Voltage (lo, = 1.6mAdc, Vcc = 4./3V} SYNC, Data, AQ-A1 5. R/W VOL ~ Vss + 04 Vde eT - - - t Power Supply Current ICC 10 160 mA Capacitance C OF (Vin =O.TaA = 25 C. b= 1MR2) LOGIC Cin _ 1O Data _ 13 AQ-A15. R/W. SYNC Cout 12 2. (in) CD tin 15 D. Cg. 30 50 D Cd _ 56 | 80 | Note: IRQ and NMI requires 3K pull-up resistors. a.COMMON CHARACTERISTICS Ciock Timing 6502, 03, 04, 05, 06, 07 Clock Timing 6512, 13, 14, 15 T Boum) c TFG ] i RSQ 24V A, (IN) 1.5V 1L5V av 4AV- 9 PWHG OL PWHZOH _. 8, OuT) |.5Vv _ PWH , B> IN; B> (OUT) RW RW ADDRESS ADDRESS FROM FROM MPU MPU DATA an ea MEMORY MEMORY $0. | SO | ARDY : RADY ~ = | SYNC | ' 1 SYNC TSYNC | | i | I f Timing for Reading Data from Memory or Peripherals Timing for Reading Data from Memory or Peripherals | | | : | R/W RYW O.8V NN O.8V appre se i ADORESS OV FROM \ 4 0 mor TE Sey Tap T DATA 2.0V DATA ADS 2.0V MPL O,8V MPL O.8V ; Tmos Twos 7 THw HW Timing for Writing Data to Memory or PeripheralsCOMMON CHARACTERISTICS | 1 MHz TIMING Electrical Characteristics: (Vcc = 5V+ 5%, Vss =O V, Ta =0-70C) Minimum clock frequency = 50 KHz CLOCK TIMING 6502, 03, 04, 05, 06, 07 CHARACTERISTIC SYMBOL | Cycle Time Toye Do (IN) Pulse Width (measured at 1.5v) PWHMq Mo (IN) Rise. Fall Time TRO, TFZo Delay Time between Clocks (measured at 1.5v) TD 21 (OUT Pulse Width (measured at 15 PWHD] 22 (OUT) Pulse Width (measured at 1.5v) PWH D1 (OUT). G2 OUT) Rise. Fal! Time TR, TF (measured Ov to 2.0v) (load '2 30 pf'%1 TTL CLOCK TIMING 6512, 13, 14,15 _ CHARACTERISTIC SYMBOL | Cycle Time Toye | Clock Pulse Width D1 PWH Zit (Measured at Ve--02V) 2 PWH @2 Fall Time, Rise Time (Measured from 0.2v to Ve--0.2V Tr, TR Delay Time between Clocks (Measured at0.2 Vj Tp READWRITE TIMING (LOAD = ITTL) _ | CHARACTERISTIC SYM BOL Read/Write Setup Time from 6500 TRWS Address Setup Time from 6500 TADS Memory Read Access Time TACC Data Stabiiity Time Period Tosy Daia Hold Time Read THR Data Hold Time Write THyw Data Setup Time from 6500 TMDS 9.Q. Setup Time Tso SYNC Setup Time from 6500 TSYNC Address Hold Time THA R/W Hold Time THRYW RDY Setup Time TRDY | 7 2 MHz TIMING MIN, TYP. MAX. _ 1QOO pf 460 92 10 6 _ _ PWHo)-20] PWHDOL PWHDOH-40; | PWHYOH-10 2D L MIEN TYP. MAX. / 3000 | _ 430 470 20 0 _ _ _ MIN | TYP. MAX. 100 300 TQO 300 975 100 10 30 60 150 200 100 360 30 60 30 60 100 MIN, TYP. MAX. UNITS a 50C of _ Ns 240 260 Ns 10 Ns D ns PWHDoO,-20] | PWHZo, ns PWHYOH-40} iPWHZOH-10! ns 25 ns MAN, TYP. MAX. SNITS so 6 | ng 215 ns 235 15 ns O ns MIN TYP. MAX. UNITS 100 150 Ns 100 150 ns 300 ns o10 ns 10 ns 30 60 ns 15 100 Ns 10 ns 175 ns 30 60 ns 30 60 ~ ns 50 f akCOMMON CHARACTERISTICS | 3 MHz TIMING | | 4 MHz TIMING (1) Electrical Characteristics: (Vcc = 5V + 5%, Vss = 0 V. Ta = 0-70 C) Minimum clock frequency = 50 KHz CLOCK TIMING 6502, 03, C4, 05, 06, 07 CHARACTERISTIC SYMBOL Cycle Time | TCYC Zo (Nj Pulse Width (measured at 1.5vi PWHq Zo (\N) Rise, Fall Time TR. TFZo Delay lime between Clocks (measured at 1 5v) Tp 21 (OUT Puise Width (measured at 1.5v) PWH@Q D2 (QUT) Pulse Width (measured at 1 Sv) PWH Zo D1 (out) 2 (oun Rise, Fall Time TR, TF (measured 8v to 2.0V) | (Load 2 3O0pf 21 TTL) |. _CLOCK TIMING 6512,13,14,15 CHARACTERISTIC SYMBOL | Cycle Time | ICYC Clock Pulse Width BI PWH 1 (Measured atVc--O2v G2 PWH @2 Fall Time, Rise Time (Measured from O.2v 10 Ver-0.2V Tre, TR Delay Time between Clocks (Measured at0QO.2v) Tp READ/WRITE TIMING (LOAD = ITTL) _ 7 CHARACTERISTIC _ SYMBOL Read/Write Setup Time from 6500 TRWS Address Setup Time from 6500 TADS Memory Read Access Time TACC Data Stability Time Period Topsy Data Hold Time Read THe Data Hold Time Write THW Data Setup Time from 6500 TMBS S.0. Setup Time TSO. SYNC Setup Time from 6500 ISYNC Address Hold Time THA R/W Hold Time THRW | RDY Setup Time TRpY hom MIN. TYP. MAX. 333 180 170 10 5 _. _ PWHYOL-20 PWH@OL PWH@oH-40| |PWH DopH-1 0 25 | MIN. YP. MAX. 333 150 160 15 0 _ _ _ 10 10 10 o0 10 10 ee (1) 4 MHz timing for 65503-6515 Is preliminary. 1/0 MIN. TYP. MAX. UNITS 250 ns 123 127 ns _ 10 ns 5 ns PWHYOL-20| | PWHYZOL Ns PWH@OH-40| |PWHYOH-10] ns 25 ns L. MIN. | FYP. MAX. UNITS oso | ns 120 ns 125 | = | ! } 15 AS 0 ns ! a | MIN | TYP. | MAX. | | UNITS) 80 80 ns 80 85 Ns 115 ns 40 ns 9 Ns 10 Ns rae 90 Ns 4Q _ _ ns | 100 Ns 1Q 30 | ons | 10 30 | Ns ike } ons |COMMON CHARACTERISTICS 6500 SIGNAL DESCRIPTION Clocks (Dy D>) The 651X requires a two phase non-overlapping clock that runs at the Vcc voltage level. The 650X clocks are supplied with an internal clock generator. Tne frequency of these clocks is externally controlled. These outputs are TTL compatible. capable of driving one Standard TTL load and 130 pf. Data Bus (D,-D,) Eight pins are used for the data bus. This is a bi-directional Dus, transferring data to and from the device and peripherals. The Outputs are tri-state buffers capable of driving one standard TTL load and 130 of. Data Bus Enabie(DBE) This TTL compatible input allows external control of the tri-state data output buffers and will enabel the microprocessor bus driver when in the high state. In normal operation DBE would be driven by the phase two (3) clock, thus allowing data output from microprocessor only during @-. During the read cycle, the data Dus drivers are internally disabled, becoming essentially an open circuit. To disable data bus drivers externally, OBE should be held low. Ready (RDY) This input signal allows the user to single cycle the microprocessor on all cycles except write cycies. A negative transition to the low state during or coincident with phase one (Z,) and up to 100ns after phase two (@;) will halt the microprocessor with the output address lines reflecting the current address being fetched. This condition will remain through a subsequent phase two (@ _) in which the Ready signal is low. This feature allows microprocessor interfacing with low speed PROMS as well as fast (Max. 2 cycte) Direct Memory Access (DMA). If Ready is low during a write cycle. it is ignored until the following read operation. Interrupt Request (IRQ) This TTL level input requests that an interrupt sequence begin within the microprocessor. The microprocessor will complete the current instruction being executed before recognizing the request. At that time. the interrupt mask bit in the Status Code Register will be examined. If the interrupt mask flag is not set. the microprocessor will begin an interrupt sequence. The Program Counter and Processor Status Register are stored in the stack. The microprocessor will then set the interrupt mask flag high so (nat no further interrupts may occur. At the end of this cycle. the Orogram counter low will be loaded from address FFFE. and program counter high trom location FFFF. therefore transferring program control to the memory vector located at these addresses. The RDY signal must be tn the high state for any interrupt to be recognized. A3K_ external resistor should be used for proper wire-OR operation. Non-Maskable Interrupt (NMI) A negative going edge on this input requests that a non-Maskable Interrupt sequence be generated within the microprocessor. NMI Is an unconditional interrupt. Following completion of the current instruction. the sequence of operations defined for IRQ will be performed, regardless of the interrupt mask flag status. The vector acdress oaded into the program counter, low and high, are locations FFFA and FFFB respectively, thereby transferring program control to the memory vector located at these addresses. The instructions loaded at these locations cause the microprocessor to branch to a non-maskable interrupt routine in memory. NMI! also requires an external 3K register to Vcc for proper wire- OR operations. Inputs IRQ and NMI are hardware interrupt lines that are sampled during@> (phase 2) and wiil begin the appropriate interrupt routine on the @, (phase 1) following the completion of the current instruction. set Overflow Fiag (S.O.) A NEGATIVE going edge on this input sets the overflow bit in the status Code Register. This signal is sampied on the trailing edge of Z,. SYNC This output line is provided to identify those cycles in which the microprocessor IS doing an OP CODE fetch. The SYNC line goes high during @, of an OP CODE fetch and stays high for the remainder of that cycle. If the RDY line is pulled low during the @, clock pulse In which SYNC went high, the processor will stop in Ils Current state and will remain in the state until the RDY line goes Nigh. In this manner, the SYNC signal can be used to control RDY to Cause single instruction execution. Reset This input is used to reset or start the microprocessor from a power down condition. During the time that this line is held low, writing to or from the microprocessor is inhibited. When a positive edge Is detected on the input, the microprocessor will immediately begin the reset sequence. After a system initialization time of six clock cycles, the mask interrupt flag will be set and the microprocessor will load the program counter from the memory vector locations FFFC and FFFD. This is the start location for program control. After Vcc reaches 4./5 volts IN a power Up routine. reset must be held low for at least two clock cycles. At this time the R/W and (SYNC) signal will become valid. When the reset signal goes high following these two ciock cycies. ihe microprocessor will proceed with the normal reset procedure detatied above.ADDRESSING MODES ACCUMULATOR ADDRESSING This form of addressing Is represented with a one byte instruction, implying an operation on the accumulator. IMMEDIATE ADDRESSING In immediate addressing, the operand is contained in the second byte of the instruction, with no further memory addressing required, ABSOLUTE ADDRESSING In absolute addressing, the second byte of the instruction specifies the eight low order bits of the effective address whi'a the third byte specifies the eight high order bits. Thus. the absolute addressing mode allows access to the entire 65K bytes of addressable memory. ZERO PAGE ADDRESSING The zero page instructions allow for shorter code and execution times by only fetching the second byte of the instruction and assuming a zero high address byte. Careful use of the zero page can result in significant increase In code efficiency. INDEXED ZERO PAGE ADDRESSING (X, Y indexing) This form of addressing Is used in conjunction with the index register and is referred to as Zero Page. X or Zero Page, Y. The effective address is calculated by adding the second byte to the contents of the index register. Since this is a form of Zero Page addressing, the content of the second byte references a location In page zero. Additionally. due to the Zero Page addressing nature of this mode, no carry is added to the high order 8 bits of memory and crossing of page boundaries does not occur. INDEX ABSOLUTE ADDRESSING (X, Y indexing) This form of addressing !s used tn conjunction with X and Y index register and is referred to as Absolute, X," and Absolute, Y. The effective address is formed by adding the contents of X and Y to the address contained in the second and third bytes of the Instruction. This mode allows the index register to contain the index or count value and the instruction to contain the base address. This type of indexing allows any location referencing and the index to modify multiple fields resulting in reduced coding and execution time. INSTRUCTION SET ALPHABETIC SEQUENCE ADS Add Memory to Accumulator with Carry AND "AND" Memory with Accumulator ASL Shift left One Bit (Memory or Accumuiaton BCC Branch on Carry Clear BCS Branch on Carry Set BEQ Branch on Result Zero Sil Test Bits in Memory with Accumulator BMI Branch on Result Minus BNE Branch on Result not Zero BPL Branch on Result Plus BRK Force Break BVC Branch on Overflow Clear BVS Branch on Overflow Set CLC Clear Carry Flag CLD Ciear Decimal Mode CLI Clear Interrupt Disable Bit CLY Clear Overflow Flag CMP Compare Memory and Accumulator CPX Compare Memory and Index X CPY Compare Memory and Index Y DEC Decrement Memory by One DEX Decrement Index X by One DEY Decrement index Y by One EOR Exclusive or Memory with Accumulator INC Increment Memory by One INX increment Index X by One INY = Increment Index Y by One JMP Jump to New Location JSR Jump to New Location Saving Return Address IMPLIED ADDRESSING !n the implied addressing mode. the address containing the operand is implicitly stated in the operation code of the instruction. RELATIVE ADDRESSING Relative addressing is used only with branch instructions and establishes a destination for the conditional branch. The second byte of the instruction becomes the operand which Is an Offset added to the contents of the lower eight bits of the program counter when the counter is set at the next instruction. The range of the offset is 128 to + 127 bytes trom the next instruction. INDEXED INDIRECT ADDRESSING In indexed indirect addressing (referred to as [{Indirect. X}, the second byte of the instruction is added to the contents of the X index register, discarding the carry. The result of this addition points to a memory location on page zero whose contents is the low order eight bits of the effective address. The next memory location in page zero contains the high order eight bits of the effective address. Both memory iocations specifying the high and low order bytes cf the effective address must be in page zero. INDIRECT INDEXED ADDRESSING In indirect indexed addressing (referred to as [Indirect. Y]), the second byte of the instruction points to a memory location in page zero. The contents of this memory location is added to tne contents of the Y index register, the result being the low order eight bits of the effective address. The carry from this addition is added to the contents of the next page zero memory location. the resuit being the hign order eight bits of the effective address. ABSOLUTE INDIRECT The second byte of the instruction contains the low order eight bits of a memory location. The high order eight bits of that memory focation Is contained in the third byte of the instruction. The contents of the fully specified memory location is the low order byte of the effective address. The next memory location contains the high order byte of the effective address which Is loaded into the sixteen bits of the program counter. LDA Load Accumulator with Memory [OX Load Index X with Memory LDY Load Index Y with Memory [SR Shift One Bit Right (Memory or Accumulaton NOP No Operation ORA OR Memory with Accumulator PHA Push Accumulator on Stack PHP Push Processor Status on Stack PLA Pull Accumulator from Stack PLP Pull Processor Status from Stack ROL Rotate One Btt Left (Memory or Accumulator ROR Rotate One Bit Right (Memory or Accumulator RT| Return from Interrupt RTS Return from Subroutine SBC Subtract Memory from Accumulator with Borrow SEC Set Carry Flag SED Set Decimal Mode SEI Set Interrupt Disable Status STA Store Accumulator in Memory OTX store index X in Memory STY Store index Y in Memory TAX ~~ Transfer Accumulator to Index xX TAY Transfer Accumulator to Indaex TSX ~ Transfer Stack Pointer to Index x TXA = Transfer tndex X to Accumulator TXS Transfer tndex X to Stack Register TYA Transfer index Y to Accumulator_ 13 COMMON CHARACTERISTICS , PROGRAMMING MODEL , PCH | PCL INSTRUCTION SETOP CODES, Execution Time, Memory Requirements 0 Q ACCUMULATOR INDEX REGISTER INDEX REGISTER | STACK POINTER | PROGRAM COUNTER PC 0 tv] fepopifajc ie-- PROCESSOR STATUS REG P CARRY ZERO KROQ DISABLE DECIMAL MODE BRK COMMAND OVERFLOW NEGATIVE TRUE RESULT ZERO 1 = DISABLE 1 = TRUE TRUE 1 = NEG ACC OMUL Niece Commedore Semiconductor Group cannot assume liability for the use of undefined OP Codes Ada MUST Be CHECKED FOR ZERC RESULT in INSTRUCTIONS IMMEDIATE | ABSOLUTE | ZERO PAGE | ACCUM. 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IMMEDIATE | ABSOLUTE | ZEAD PAGE | ACCUM IMPLIEG (ND. x DL Y =| Z PAGE Y ABS, ABS neLarwe | inpmect | z. pace y | CONDITION CODES MNEMONIC OPERATION sie fa frets fe foc cept ds forge fs jes a dees, fs lap) ORL Js Lop a(TPlt: fe JOelti de kel paedh Foo 0 FY De | ae * Jaz) 2]2 lathe] 3 fan] 3 | BE} + | 3 eG, spo fe we - - - i m ( bt yo ft, 748) 2) 2 AC) 4] 3 [Aap AGS Ba] 4]? (BC Ts) 3 i i : 5 GR 2-[ Oke C SFY A )3 fae] s | 2 faa] c SHY AP OSE 7 43 dy 8 - - - . . 5 "COOPERATION Fat? | - = - = = . A . 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AR 1 TT SIF Page BOUNOGAYW IS CROSSED Hla * * ADC y EXCLUSIVE OR NJ NO CYCLES 2 ACC i TC cM iF BRANCH OCCURS TO SAME PAGE r INDE SUBRTAAC , MOCHIFIED f NO BYTES AcE 2 TO UNH BRANCH TCO CURS TO DIFFEREN PAGE o ACCUMULATOR AND - NOT MODIFIED pd CARRS MOT BORR Cs Mo MEMORY PER EFFECTIVE ADDRESS , OR A. MEMORY BIT 7 HIF IN CECMAL MODE FLAG IS INVAL IE Me MEMCRY PER STACK OONTER Ms MEMORY SIT 6 apn SVSS RDY D (OUT [RO N.C. NMI SYNC RES vss IRQ VCC Be I b> b F- Mp -)] OD Gs fF fa Ts y- ~4 G:F & Ge Mh 8 g mks (C4 f._ Go PG A15 Ai4 Al3 Al2 VSS 650240 Pin Package Features of 6502 e 65K Addressable Bytes of Memory (A0-A1 9) @ |RQ Interrupt On-the-chip Clock TTL Level Single Phase Input RC Time Base Input Crystal Time Base Input SYNC signal (can be used for single instruction execution) RDY signal (can be used to halt or single cycle execution) Two Phase Output Clock for Timing of Support Chips @ NMI interrupt Bo (OUT Do (IN) Ry Ww DO D1 D2 D3 D4 D5 D6 D7 AV A10 AQ go (OUT) Qo (EN) RV DO | De U3 D4 D5 Bis D/ Ale All AiQ D> OUT Diy ini R, W AIQ 650328 Pin Package Features of 6503 e 4k Addressable Bytes of Memory (AO0-A1 1} @ On-the-chip Clock @ (RQ Interrupt @ NMI Interrupt @ 8 Bit Bidirectional Data Bus 650428 Pin Package Features of 6504 8K Addressable Bytes of Memory (AQO-Aj 2} @ On-the chip Clock |RQ Interrupt e 8 Bit Bidirectional Data Bus 650528 pin Package Features of 6505 e 4k Addressable Bytes of Memory (AQ-A1 1} On-the-chip Clock |RQ Interrupt @ RDY Signal 8 Bit Bidirectional Data Bus 10D> (OUT) 0 (IN) 650628 Pin Package iV ~ Features of 6506 D2 @ 4k Addressable Bytes of Memory (AQ-A1 1) D3 @ On-tne-chip Clock Dd |RQ Interrupt D5 Two ohase output clock for timing at D6 support chips D7 e 8 Bit Bidirectional Data Bus AV A10 Ag j 2 3 4 5 6 f 9 | D> (OUT; Zo (IN) . RW 650728 Pin Package DU D1 Features of 6507 D2 @ 8K Addressable Bytes of Memory (AO-A1 2) D3 On-the-chip Clock RES VSS RDY VCC AO AY A2 AS 2 RDY Signal at 79 e 8 Bit Bidirectional Data Bus AS Bis AG Di AT Al2 Ad Al AQ A10 ee VSS 1 = RES RDY 2 = Bo Ou) 6512-40 Pin Package By (IN) 3 = so IRQ 4 = Bo (IN Features of 6512 4. Se 65K Addressable Bytes of Memory (A0-A15) NMI 0 mI NC SYNC 7 RW @ {RQ Interrupt vCC g ~ OC @ NM! Interrupt Qg 3] e RLY Signal a : > Dp: @s Bit Bidirectional Data Bus AD 11 = D3 SYNC signal | AG 12 De Two phase clock input AS 13 DS Data Bus Enable AS 14 = Do AG 1D 3 D7 AT lo = Aids A8 V = Ald AQ 18 = AIS ALG 1g Ai2 Alt ZU m= VSS 11RES VSS By (IN) D2 \IN} 651328 Pin Package IRQ RiW NMI DU Features of 6513 VCC 01 AO 02 4k Addressable Bytes of Memory {A0-Ai 1) Al D3 @ Two phase clock input A2 D4 |RQ Interrupt A3 D5 @ NM! Interrupt A4 Do e 8 Bit Bidirectional Data Bus AS D7 AG Al) A7 A10 A8 Ag VSS RES ZB (IN) 2 B> (iN} IRQ 3 R/W 651428 Pin Package VCC 4 DO AO . DI Features of 6514 Al 6 D2 AD 7 D3 e 8K Addressable Bytes of Memory (AO-A1 2) A3 8 D4 Two phase clock inpul Ad g D5 @ (RQ Interrupt AS 10 D6 8 Bit Bidirectional Data Bus AG iF D7 A7 12 Al2 A8 13 Al Ag 14 A10 VSS RES RDY 2 Bo iIN) 651528 Pin Package J) (IN) =H 3 Ry W IRQ 4 DO Features of 6515 VCC 5 DI AO 6 D2 @ 4K Addressable Bytes of Memory (AO0-A1 1} AG 7 D3 @ Two phase clock input AD 3 D4 {RQ Interrupt A3 9 D5 RDY Signal Ad 10 Db 8 Bit Bidirectional Data Bus AS 1 D AG 12 All A? 13 A10 A8 14 AY COMMODORE SEMICONDUCTOR GROUP reserves the right to make changes to any products herein to improve reliability, function or design. COMMODORE SEMICONDUCTOR GROUP does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. 12